Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include one or more semiconductor dies mounted on a substrate and encased in a protective covering. The semiconductor dies include functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the semiconductor die to be connected to higher level circuitry. Within some packages, semiconductor dies can be stacked upon and electrically connected to one another by individual interconnects placed between adjacent semiconductor dies. In such packages, each interconnect can include a conductive material (e.g., solder) and a pair of contacts on opposing surfaces of adjacent semiconductor dies. For example, a metal solder can be placed between the contacts and reflowed to form a conductive joint.
One challenge with such traditional packages is that variations in heat and/or force can exist during a bonding operation to form the interconnects. This can affect the quality of the interconnects, for example, by leading to an open-circuit across the solder joints, high ohmic resistance across the solder joints, solder bridging between nearby interconnects, etc.